Working for a cutting edge semiconductor company, I have a brand-new Senior Digital Design Verification opportunity to work on the latest high-speed communication ASIC technologies.
You will be part of key R&D projects for complex IP - working closely with designers, architects and other verification engineers in the wider business.
110-120k CHF
Must have skills:
1. University degree - BSc / MSc / PhD in Electronics, Microelectronics, Physics or Computer Science
2. Industry experience in digital verification - for FPGA / ASIC (VHDL and / or Verilog, System verilog)
3. Good language & communication skills in English
4. Strong coding skills - python / C / C++ / System C
5. UVM environments, libraries and complex test-benches for digital IPs
Bonus / "nice-to-have" skills:
6. Definition of complex digital architecture
7. High-speed digital connectivity and protocols - Serdes, ethernet, USB, PCIe, AMBA / AXI, MAC, PHY, cache coherency - MESI
8. Testing / validation
9. Matlab / Simulink modelling experience
10. confident software coding skills - C++ / python etc
11. formal / software verification - jasper gold, onespin, SVA - system verilog assertions
12. language & communication skills in French