Senior Analog IC Layout Engineer with finFET experience Salary: Very Attractive Rate
Location: N/A
Contract
Minimum 7 year's experience in Analog IC Layout
Experience working on High Speed Layout
Experience working on speeds up to or past 25 Gb/ sec
Experience working on finFET technology/ TSMC down to 16nm
Experience using Cadence tools
Senior Analog Layout Engineers - 4-5 Engineers Minimum 7 year's experience in Analog IC Layout
Experience working on High Speed Layout
Experience working on speeds up to or past 25 Gb/ sec
Experience working on finFET technology/ TSMC down to 16nm
Experience using Cadence tools
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