Senior Analog IC Layout Engineer with fin FET experience Salary: Very Attractive Rate Location: N/A Contract Minimum 7 year's experience in Analog IC Layout Experience working on High Speed Layout Experience working on speeds up to or past 25 Gb/ sec Experience working on fin FET technology/ TSMC down to 16nm Experience using Cadence tools Senior Analog Layout Engineers - 4-5 Engineers Minimum 7 year's experience in Analog IC Layout Experience working on High Speed Layout Experience working on speeds up to or past 25 Gb/ sec Experience working on fin FET technology/ TSMC down to 16nm Experience using Cadence tools Chipright – Your Partner in finding that next job – Call us on +353 91 444168 or Email annette.burke@chipright.com
#J-18808-Ljbffr